64-bit CPU

[Henry Spencer]

On Wed, 15 Sep 2004, Sergey Kuznetsov wrote:
> There is no any decrease in speed, because the bus also 64-bit, it means 
> it can deliver 64-bits of data in one-two CPU clocks.

There's no connection between the CPU instruction/register width and the
bus width, especially when there's a cache in between.  PC memory buses
have been 64 bits wide since the Pentium I, and if I've understood the
jargon correctly, today's systems with dual-channel DDR memory have
effectively a 128-bit memory bus.

                                                          Henry Spencer
                                                       henry-lqW1N6Cllo0sV2N9l4h3zg at public.gmane.org

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