[GTALUG] MP BIOS Toshiba - semi revival

[R. Russell Reiter]

<snip>.

>So yes VLIW is more efficient if you order the instructions at compile
>time.  Too bad in reality that has turned out to be impossible in the
>general case.  Makes wonderful DSP/GPU/other stream processing chips
>though.

I note that Transmetta's Caruso uses code-morphing to achieve a kind of bi-polar state. I don't really know if it is truly comfortable with VLIW or not.

I think it is well within the realm of possibilities that an ILP environment could offer this as a trusted feature; two channel booting. 

That is, there are two channels defined and each boots an identical copy of an operating system to a steady ready state, hopefully from the same clock tic. Only one channel exposes itself as user space, the other acts as a dynamic checkum of the kernelspace. 

Humans may be defined as left or right brained, why not computers. 

This is sort of like the parallel RAS proposed to deal with current issues with the quality of manufacture of ram and resulting  reliability issues. Also notwithstanding the amount of heuristics which are needed at machine level.

I'll omit my theories of EM containment in near fields which affect ram and cause bit flips for the moment.

I think machine learning is real and that capacity planning does take this into account. 

Given the exponential growth of IT infrastructure in this wired world; the id, the ego and the superego of the internet are well documented. 

So IMHO when properly co-ordinated, the future becomes now and even if it is only in my imagination, I can still have fun with it.


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