poll: problems with MTRRs?

Tue Mar 17 18:04:06 UTC 2009

On Tue, Mar 17, 2009 at 11:23:39AM -0400, D. Hugh Redelmeier wrote:
> | From: Lennart Sorensen <lsorense-1wCw9BSqJbv44Nm34jS7GywD8/FfD2ys at public.gmane.org>
> | Reply-To: tlug-lxSQFCZeNF4 at public.gmane.org
> | To: tlug-lxSQFCZeNF4 at public.gmane.org
> | Subject: Re: [TLUG]: poll: problems with MTRRs?
> | 
> | On Mon, Mar 16, 2009 at 09:28:51PM -0400, D. Hugh Redelmeier wrote:
> 
> | > PCI addresses are 64 bits but most devices only use 32-bit addresses.
> | > On ordinary (non-64-bit) PCI, passing 64-bit addresses takes two
> | > transfers.  I don't know about PCIe.
> | 
> | No PCI can be 32 or 64bit.  If a device is 32bit then it can only address
> | 32bit addresses at all.  Many devices are this way.  It's simpler and
> | cheaper to implement them with only room for 32bit addresses.  Why intel
> | decided that in IDE mode it should be 32bit and in AHCI it should be
> | 64bit capable I have no idea.  Maybe PCI IDE was simply always defined
> | as 32bit only.  At least on the current ICH10 series they finally made
> | AHCI officially available on both the raid and nonraid versions.
> 
> Even with a 32-bit PCI bus, 64-bit addresses can be supported.
> Look at http://pinouts.ru/Slots/PCI_pinout.shtml

Yes.  I meant to say "If a device is 32bit internally".  The bus width
isn't relevant to the issue.

>     Although it is not widely implemented, PCI supports 64-bit addressing.
>     Unlike the 64-bit data bus option which requires a longer connector
>     with an additional 32-bits of data signals, 64-bit addressing can be
>     supported through the base 32-bit connector. Dual Address Cycles are
>     issued in which the low order 32-bits of the address are driven onto
>     the AD[31:0] signals during the first address phase, and the high
>     order 32-bits of the address (if non-zero) are driven onto the
>     AD[31:0] signals during a second address phase. The remainder of the
>     transfer continues like a normal bus transfer.
> 
> On the 64-bit PCI bus, there are 64 AD lines so that a 64-bit address
> can be transmitted in one cycle.
> 
> My *guess* is that any 32-bit device could choose to support 64-bit
> addresses but the computer would not need to handle this if it chose
> never to program any DMAs beyond 4GiB.

Unfortunately most 32bit PCI devices seem to not have chosen to support
64bit addresses.  I guess since most PCs still run 32bit windows
there hasn't been much demand.  Server grade hardware may have started
supporting it sooner since they often use PAE or even 64bit software now.

> | Unfortunately, while AMD CPUs with their onboard memory controller also
> | included an IOMMU on almost all of the chips (some early ones didn't
> | have it as far as I recall), intel did not do the same in their chipsets,
> | except for some server chipsets.  Hence my Core2Quad + P35 chipset has
> | no IOMMU and has to do a softIOMMU using a bounce buffer.
> 
> I wonder why.  Intel seems to be really stingy about VT and VT-d
> compared with AMD.  I guess that Intel can use this to price
> differentiate but AMD is kind of desperate for any sale.

Intel has volumes enough to justify lots of part variations.  Just look
at their "Don't use ICH9 in AHCI mode" issue.

AMD's volumes are low enough that fewer actual die designs is preferable.

> I don't remember any Athlon 64 without an IOMMU.  Not that I would
> necessarily know.  Do you have any more solid information?

Well I have an Athlon 64 3500+ under my desk which is one of the early
ones that does not support AMD-V and hence has no IOMMU.  It is an old
socket 939 chip.  It only has 1GB of ram though so it never mattered.
The other disadvantage that CPU has is that you can not run a 64bit
guest in a virtual machine on it in say vmware due to the lack of AMD-V.

The Cx, Dx, and Ex spec Athlon 64's don't have AMD-V.  The Fx, Gx and
newer do.

As far as I can tell, no socket 754 or 939 Athlon64 had the IOMMU.  I am
not entirely convinced that is right though (and it is from wikipedia
so who knows).  All AM2 chips should have it.

On the opteron's, it seems the 1xx doesn't have it, while the 2xx, 8xx,
1xxx, 2xxx and 8xxx all have it.

I am pretty sure some of the socket 939 chips had some virtualization
support that predates the AMD-V stuff, which allowed at least the 64bit
guests to work in vmware, but didn't really do much performance wise.
AMD-V apparently is much better.

-- 
Len Sorensen
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