poll: problems with MTRRs?

[D. Hugh Redelmeier]

| From: Lennart Sorensen <lsorense-1wCw9BSqJbv44Nm34jS7GywD8/FfD2ys at public.gmane.org>
| Reply-To: tlug-lxSQFCZeNF4 at public.gmane.org
| To: tlug-lxSQFCZeNF4 at public.gmane.org
| Subject: Re: [TLUG]: poll: problems with MTRRs?
| 
| On Mon, Mar 16, 2009 at 09:28:51PM -0400, D. Hugh Redelmeier wrote:

| > PCI addresses are 64 bits but most devices only use 32-bit addresses.
| > On ordinary (non-64-bit) PCI, passing 64-bit addresses takes two
| > transfers.  I don't know about PCIe.
| 
| No PCI can be 32 or 64bit.  If a device is 32bit then it can only address
| 32bit addresses at all.  Many devices are this way.  It's simpler and
| cheaper to implement them with only room for 32bit addresses.  Why intel
| decided that in IDE mode it should be 32bit and in AHCI it should be
| 64bit capable I have no idea.  Maybe PCI IDE was simply always defined
| as 32bit only.  At least on the current ICH10 series they finally made
| AHCI officially available on both the raid and nonraid versions.

Even with a 32-bit PCI bus, 64-bit addresses can be supported.
Look at http://pinouts.ru/Slots/PCI_pinout.shtml

    Although it is not widely implemented, PCI supports 64-bit addressing.
    Unlike the 64-bit data bus option which requires a longer connector
    with an additional 32-bits of data signals, 64-bit addressing can be
    supported through the base 32-bit connector. Dual Address Cycles are
    issued in which the low order 32-bits of the address are driven onto
    the AD[31:0] signals during the first address phase, and the high
    order 32-bits of the address (if non-zero) are driven onto the
    AD[31:0] signals during a second address phase. The remainder of the
    transfer continues like a normal bus transfer.

On the 64-bit PCI bus, there are 64 AD lines so that a 64-bit address
can be transmitted in one cycle.

My *guess* is that any 32-bit device could choose to support 64-bit
addresses but the computer would not need to handle this if it chose
never to program any DMAs beyond 4GiB.

| Unfortunately, while AMD CPUs with their onboard memory controller also
| included an IOMMU on almost all of the chips (some early ones didn't
| have it as far as I recall), intel did not do the same in their chipsets,
| except for some server chipsets.  Hence my Core2Quad + P35 chipset has
| no IOMMU and has to do a softIOMMU using a bounce buffer.

I wonder why.  Intel seems to be really stingy about VT and VT-d
compared with AMD.  I guess that Intel can use this to price
differentiate but AMD is kind of desperate for any sale.

I don't remember any Athlon 64 without an IOMMU.  Not that I would
necessarily know.  Do you have any more solid information?
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