What is "dual-channel DDR"?

Andrew Hammond ahammond-swQf4SbcV9C7WVzo/KQ3Mw at public.gmane.org
Wed Mar 16 21:09:47 UTC 2005


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I'm sorry, but PAE works exactly as Chris described below. If anything,
he's too gentle describing the cost as "pretty appreciable". Consider
that for architectures which support this egregious hack, all the IO has
to pass over the Front Side Bus. The FSB is a bottleneck on modern
single processor systems and only gets worse with multiple processors.

On a Xeon system (EM64T or otherwise) an inbound IO now follows this
pattern:
1) northbridge -> FSB -> memory
2) context switch triggers page switch: memory -> FSB -> PAE controller
- -> FSB -> memory
3) memory -> FSB -> CPU (kernel)
4) CPU -> FSB -> memory
5) memory -> FSB -> PAE -> FSB -> memory
5) memory -> FSB -> CPU (application)

So, data in the bounce buffer (since Chris has us using BSD terminology)
goes through the FSB a total of 8 times. And this is assuming that
there's no cache stupidity due to processes migrating between CPUs.
EM64T makes the Xeon a 64bit chip in the same way that putting racing
strips and a big ass wing on the back of a '89 Pinto makes it a race car.

PAE is NOT supported on Opterons. The hardware to do paging just isn't
there. Running a 32bit OS on an Opteron with >4G of memory would be
foolish since the extra memory is inaccessible. There are some merits to
running 32bit code on an Opteron, which is what I assume you're talking
about here. Both SuSE and Redhat support the lib / lib64 convention.
However pointer storage space is, for most programs, not worth
considering. The real win (such as it is) from running in 32bit is that
the binaries are about 10% smaller on average and hence load from disk a
little quicker and consume a little less memory IO in operation.

- --
Andrew Hammond    416-673-4138    ahammond-swQf4SbcV9C7WVzo/KQ3Mw at public.gmane.org
Database Administrator, Afilias Canada Corp.
CB83 2838 4B67 D40F D086 3568 81FC E7E5 27AF 4A9A


Lennart Sorensen wrote:
| On Wed, Mar 16, 2005 at 12:30:19PM -0500, Christopher Browne wrote:
|
|>PAE requires that I/O goes into "bounce buffers" that must be copied
|>to/from user process memory.
|>
|>That's an extra set of memory copies that have a pretty appreciable
cost...
|
|
| Well true, and also true on Xeon EM64T in 64bit mode, but not the case
| on AMD64 in 64bit mode, so yeah it does help on the amd systems, just
| not on the intel systems.  So I guess it is a matter of the tradeoff
| between that and the extra memory used by pointers and the advantages
| some programs get from true 64bit arithmetic in the cpu.
|
| Lennart Sorensen
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