Hello, been a while, dual CPU mobos

[Peter L. Peres]

On Thu, 9 Sep 2004, Lennart Sorensen wrote:

> On Thu, Sep 09, 2004 at 12:01:58PM -0400, Michael Laccetti wrote:
>> P4s rely on their raw speed to keep them competitive, because of their
>> extremely long pipeline.  The newer versions are at least 20 stages, perhaps
>> even longer.  AMD, and the P3s/Pentium Ms (not Pentium 4M) have a short
>> pipeline.  Of course, they can't scale to be as speedy.  My Pentium M 1.7
>> competes quite well with my Pentium 4 2.8 in terms of compilation times, the
>> only thing that holds it back is the DDR 333 vs. the DDR 480 (yay
>> overclocking) in my workstation.  That, and the laptop HD is quite a bit
>> slower than the workstation.
>
> Current "prescott" P4's have 31 stage.  Previous generation was 20
> stage.
>
> This may explain why same clock speed "prescott" chips have often been
> slower than the "northwood" chips, although having larger cache in
> general helped out in other cases.  Very confusing and hard to
> generalize performance from I guess.
>
> Opteron/Athlon 64 currently runs 12 stage pipeline as far as I know.
>
> I know which one I want.

Is it a secret ? ;-)

Question: if the pipeline length is so important then these cpus should 
work better with 'flattened' code (no jumps, no loops). Do the speed tests 
just so happen to be compiled flattened ? I.e. do the chip makers add 
pipeline length to look better in tests or to give better all-round 
performance. I suspect that code with very short runs between jumps and 
loops (such as code compiled for size optimisation) will run relatively 
slowly on such a cpu. True ?

Peter
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