[GTALUG] interesting new approach to forking

[Russell Reiter]

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>
> Well intel has tried using VLIW 3 times now, and (mostly) failed 3 times.
> Only seems to have ever been successful in DSP designs (hence the "mostly"
> for intel, with the i860 being fairly successful in DSP use, but not as
> a general purpose CPU).

Three billion transistors require a mighty robust memory management
subsystem. Given the development costs of these chip sets and other
factors of parallel advancements in existing architectures, a few
false starts are to be expected. Who knows maybe all this belongs in
the tomorrow file.

Instruction replay RAS and other improvements for checking and
correcting errors, are most certainly desirable features. Fine grained
exit status is essential for lockstepping cache threads and compile
time predication looks like it could be efficient enough for reducing
transport delay. Just need better ram with fewer flaws or perhaps
parallel RAS and journal the bad bits. ECC or not its the uncommon
errors which need to be predicated.

So now the problem is not limited to things like voltage flux, it's
far field interference like background radiation which tend to flip
the bits.