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mike-DlQxw/23Tq2aMJb+Lgu22Q at public.gmane.org mike-DlQxw/23Tq2aMJb+Lgu22Q at public.gmane.org
Tue Feb 15 19:24:19 UTC 2005


> On Tue, Feb 15, 2005 at 11:49:16AM -0500, mike-DlQxw/23Tq2aMJb+Lgu22Q at public.gmane.org wrote:
>> What makes you think em64t is a 32bit core?
>
> The performance it shows in 64bit mode, and that intel kept telling
> people that no one needed 64bit, and then suddenly had it.  Sure didn't
> sound like time for a new design, just a patch of more extensions to the
> addressing parts of the cpu.

IIRC, the P4's all have a risc core with a translation layer for
converting the actual instructions into a series of micro-ops.  I really
doubt the core itself isn't 64bit, and one of the problems that has
plagued the P4 is the fact that the pipe-line within this core is very
long, leading to latentcy due to pipeline stalls.

Adding em64t to the mix becomes simply an issue of translating the x86-64
instructions to the proper risc micro-ops.

>
> Intel also only claims it is the same chip with 64bit addressing
> extensions.  They don't claim it is a 64bit cpu.  it can allocate more
> than 4GB ram to a single application, which may help some databases, but
> it doesn't operate other 64bit things as fast as 32bit.  It also uses a
> bounce buffer in hardware to do 64bit addressing to hardware addresses,
> which adds a bit of latency, which the amd64 doesn't have or need.
>

This is only an issue if your hardware peripherals only support < 64
addressing.  PCI-X support 64 bit addressing, though a lot of cards don't
actually support 64 bit addresses.  Out of those that do, many are
limitted to buffers that don't cross a modulo 4GB barrier.  This is easily
handled in the driver though.

The reality is that an IOMMU is a short-gap measure for not using dma
bounce buffers when using cheaper hardware.

>> Um, I hope you mean AMD's integration of the northbridge on die, which
>> happens to have an IOMMU.
>
> Well having the memory controller certainly is part of making it run
> faster.  Using hypertransport as the cpu to cpu link and cpu to other
> chipset component link seems sensible.  The alpha based bus of the
> athlon was nice, but hypertransport seems like an even better design
> choice.
>
> I personally never liked the P4 from the day I saw the first reviews of
> it's design, it just seemed like a step backwards from the P3.  The
> Pentium M on the other hand (which continues the P6 core from the PPro
> and P2/P3 is much more impresive.  I hope some day it will actually
> officially become a desktop CPU and the P4 can go where it belongs, and
> hopefully intel will never let marketing design their CPUs again.
>
> Lennart Sorensen
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