64-bit CPU

[Henry Spencer]

On Thu, 16 Sep 2004, Andrej Marjan wrote:
> I haven't thought about it much, but just off the cuff, it seems to me 
> that given equivalent OOO infrastructure supporting an ISA with few 
> architectural registers and an ISA with many architectural registers, 
> the latter should still perform better, even though the former performs 
> better than a register starved ISA without the OOO bits would.

Generally speaking, other things being equal (a large assumption), yes. 
If nothing else, the register-starved ISA is using a fair number of
instruction bits to address the memory locations that are being magically
reinterpreted as internal registers, and a fair bit of hardware to do the
magic and deal with the possibility of the swept-under-the-carpet memory
accesses doing something undesirably exciting, and almost all of that goes
away with more registers.  Registers in quantity are good. 

> That's more or less what you get with AMD64: there are still rename 
> registers and the works in 64 bit mode, but there are also 8 more GPRs...

Hmm, pity it's only 8.  16 or 32 would have been nice.

                                                          Henry Spencer
                                                       henry-lqW1N6Cllo0sV2N9l4h3zg at public.gmane.org

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