64-bit CPU

[Andrej Marjan]

Lennart Sorensen wrote:

>There has to be more to it than that.  I guess for one, 64bit integer
>math can be done natively rather than whatever x86 used to do (I don't
>think x86 32bit chips have done 64bit addition and such natively,
>I figure they had some way around it that chopped it up and manipulated
>it a bit in the compiler.)  Then again maybe it is just having a few
>more registers helping out, although the P6 architecture's register
>renaming (which has a lot more than 8 registers inside the chip) used
>in the speculative execution and out of order execution already helps many
>such programs run faster than they should on an 8 register architecture.
>  
>

Hmm.. interesting. I had always assumed that MMX allowed you to do 64 
bit integer arithmetic directly, but based on a bit of googling, I can' 
find any arithmetic support for "quadwords", only for "dwords". SSE 
doesn't add this support either. Does SSE2?

I haven't thought about it much, but just off the cuff, it seems to me 
that given equivalent OOO infrastructure supporting an ISA with few 
architectural registers and an ISA with many architectural registers, 
the latter should still perform better, even though the former performs 
better than a register starved ISA without the OOO bits would.

That's more or less what you get with AMD64: there are still rename 
registers and the works in 64 bit mode, but there are also 8 more GPRs, 
meaning compilers can be less hackish, the cpu needs to do less work 
rewriting all those load/store requests, etc. So the cpu can waste less 
effort working around the ISA.
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